1. Field of the Invention
The invention relates to a method for locally polishing a semiconductor wafer.
2. Background Art
Semiconductor wafers conventionally used include silicon wafers, substrates with layer structures such as SiGe (silicon-germanium) derived from silicon, or SOI, SGOI or GeOI wafers. These semiconductor wafers, particularly SOI and SiGe wafers, are intended for the most demanding of applications, in particular for the production of ultramodern microprocessors.
SOI (“silicon on insulator”) wafers are generally produced by transferring a silicon wafer from a so-called “donor wafer” to a supporting wafer (“handle wafer” or “base wafer”). Methods for producing SOI wafers by means of transferring a silicon wafer are known, for example, by the names Smart Cut® (EP 533551 A1) or Genesis Process®. Another method is described in WO 03/003430 A2. SOI wafers comprise a supporting wafer and a silicon cover layer (“top layer” or “device layer”) which is connected to the latter and represents the so-called active layer that is intended for the production of electronic components. Either the complete supporting wafer consists of an electrically insulating material such as glass or sapphire, or the silicon cover layer is connected to the supporting wafer via an electrically insulating interlayer, for example consisting of silicon oxide (in which case the interlayer is referred to as a “buried oxide layer”, BOX). In the latter case the supporting wafer does not have to be an insulator, and it may for example be a semiconductor wafer, preferably a silicon wafer.
In the prior art, besides the transfer method described above, SOI (“silicon on insulator”) structures are also conventionally produced by means of the so-called SIMOX (“separation by ion implantation of oxygen”) process. In the SIMOX method, oxygen is implanted at high doses into a silicon substrate which is subsequently heat-treated and oxidized at high temperatures (>1200° C.) in order to generate a buried oxide layer in the silicon substrate.
Similarly, SIMOX and layer transfer methods are also suitable for the production of SGOI (“silicon/germanium on insulator”) and/or GeOI (“germanium on insulator”) structures.
SiGe layers with a high proportion of germanium, also referred to as virtual substrates, are employed inter alia for the production of biaxially strained silicon. The strain of the silicon lattice leads to an increased mobility of charge carriers, and is used in particular to make CMOS components available which have better performance than those having an unstrained silicon channel.
Virtual substrates may in principle be deposited directly on a monocrystalline silicon substrate, for example a silicon semiconductor wafer. With this procedure, however, defects such as misfit dislocations and threading dislocations are formed in large numbers. Threading dislocations and their accumulations (“pile-ups”) extend to the surface of the virtual substrate and also to the surface of a strained layer of silicon deposited on the virtual substrate. Attempts have therefore been made to find a way of limiting the density of threading dislocations and their pile-ups. Such limitation can be achieved by initially depositing a graded SiGe buffer layer, in which the atomic fraction of germanium increases linearly (“linear grading”) or in the steps (“terrace grading”). An SiGe layer with a constant germanium content is finally deposited on the SiGe buffer layer, and in the relaxed state forms the virtual substrate.
The semiconductor wafers described here must also satisfy the most stringent of requirements in terms of their geometry. Essentially, the requirements are given by the internationally agreed “Technology Roadmap for Semiconductors” (ITRS), which is subject to an annual review. For example the 22 nm technology, which places increased requirements on geometry, planarity, nanotopology etc., is currently in development. In each case, the aim of the next technology generation (the 22 nm technology will be followed by the 16 nm design rule) is higher switching speeds, higher clock rates and higher integration densities of the microelectronic components. The production methods have to accommodate these increased requirements, so that all the wafer fabrication steps must be adapted accordingly and often replaced by other, new processes.
SiGe and SOI wafers, which are expected to become very important in the future, entail additional problems which the present invention addresses.
In the layer transfer method described above, the donor wafer employed should conventionally be reusable. After separation of the donor wafer, however, steps are found at the edge of the wafer which would need to be eliminated before reusing the wafer (in order to transfer a further silicon layer).
In SiGe technology, the problem arises that there is also SiGe on the frontside of a wafer which is coated with heavily doped SiGe on its backside. When depositing epitaxial layers, material is often also deposited on the side which is not to be coated. This may even occur during the conventional deposition of an epitaxial Si layer on an Si wafer, which in this case is observable as thickening at the edge.
Furthermore, many semiconductor wafers exist in concavely or convexly polished form. An example which may be mentioned here is a wafer being thicker at the edge than in its inner region, or at the center of the wafer.
In the described cases, it would be desirable to eliminate these edge steps, the undesired coating in the edge region or the undesired thickness increase in the edge region.